PIC18F2321 |
|
CONFIG1H (address:0x300001, mask:0x07) |
|
OSC -- Oscillator |
|
OSC = LP |
0xF0 |
LP Oscillator. |
|
|
OSC = XT |
0xF1 |
XT Oscillator. |
|
|
OSC = HS |
0xF2 |
HS Oscillator. |
|
|
OSC = RC |
0xF3 |
External RC oscillator, CLKO function on RA6. |
|
|
OSC = EC |
0xF4 |
EC oscillator, CLKO function on RA6. |
|
|
OSC = ECIO |
0xF5 |
EC oscillator, port function on RA6. |
|
|
OSC = HSPLL |
0xF6 |
HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1). |
|
|
OSC = RCIO |
0xF7 |
External RC oscillator, port function on RA6. |
|
|
OSC = INTIO2 |
0xF8 |
Internal oscillator block, port function on RA6 and RA7. |
|
|
OSC = INTIO1 |
0xF9 |
Internal oscillator block, CLKO function on RA6, port function on RA7. |
|
|
FCMEN -- Fail-Safe Clock Monitor Enable bit |
|
FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
|
|
FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
|
|
IESO -- Internal/External Oscillator Switchover bit |
|
IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
|
|
IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
|
|
CONFIG2L (address:0x300002, mask:0x1F) |
|
PWRT -- Power-up Timer Enable bit |
|
PWRT = ON |
0xFE |
PWRT enabled. |
|
|
PWRT = OFF |
0xFF |
PWRT disabled. |
|
|
BOR -- Brown-out Reset Enable bits |
|
BOR = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
|
|
BOR = SOFT |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
|
|
BOR = NOSLP |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
|
|
BOR = ON |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
|
|
BORV -- Brown-out Reset Voltage bits |
|
BORV = 0 |
0xE7 |
Maximum Setting. |
|
|
BORV = 1 |
0xEF |
|
|
|
BORV = 2 |
0xF7 |
|
|
|
BORV = 3 |
0xFF |
Minimum Setting. |
|
|
CONFIG2H (address:0x300003, mask:0x1F) |
|
WDT -- Watchdog Timer Enable bit |
|
WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
|
|
WDT = ON |
0xFF |
WDT enabled. |
|
|
WDTPS -- Watchdog Timer Postscale Select bits |
|
WDTPS = 1 |
0xE1 |
1:1. |
|
|
WDTPS = 2 |
0xE3 |
1:2. |
|
|
WDTPS = 4 |
0xE5 |
1:4. |
|
|
WDTPS = 8 |
0xE7 |
1:8. |
|
|
WDTPS = 16 |
0xE9 |
1:16. |
|
|
WDTPS = 32 |
0xEB |
1:32. |
|
|
WDTPS = 64 |
0xED |
1:64. |
|
|
WDTPS = 128 |
0xEF |
1:128. |
|
|
WDTPS = 256 |
0xF1 |
1:256. |
|
|
WDTPS = 512 |
0xF3 |
1:512. |
|
|
WDTPS = 1024 |
0xF5 |
1:1024. |
|
|
WDTPS = 2048 |
0xF7 |
1:2048. |
|
|
WDTPS = 4096 |
0xF9 |
1:4096. |
|
|
WDTPS = 8192 |
0xFB |
1:8192. |
|
|
WDTPS = 16384 |
0xFD |
1:16384. |
|
|
WDTPS = 32768 |
0xFF |
1:32768. |
|
|
CONFIG3H (address:0x300005, mask:0x83) |
|
CCP2MX -- CCP2 MUX bit |
|
CCP2MX = RB3 |
0xFE |
CCP2 input/output is multiplexed with RB3. |
|
|
CCP2MX = RC1 |
0xFF |
CCP2 input/output is multiplexed with RC1. |
|
|
PBADEN -- PORTB A/D Enable bit |
|
PBADEN = DIG |
0xFD |
PORTB<4:0> pins are configured as digital I/O on Reset. |
|
|
PBADEN = ANA |
0xFF |
PORTB<4:0> pins are configured as analog input channels on Reset. |
|
|
LPT1OSC -- Low-Power Timer1 Oscillator Enable bit |
|
LPT1OSC = OFF |
0xFB |
Timer1 configured for higher power operation. |
|
|
LPT1OSC = ON |
0xFF |
Timer1 configured for low-power operation. |
|
|
MCLRE -- MCLR Pin Enable bit |
|
MCLRE = OFF |
0x7F |
RE3 input pin enabled; MCLR disabled. |
|
|
MCLRE = ON |
0xFF |
MCLR pin enabled; RE3 input pin disabled. |
|
|
CONFIG4L (address:0x300006, mask:0x85) |
|
STVREN -- Stack Full/Underflow Reset Enable bit |
|
STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
|
|
STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
|
|
LVP -- Single-Supply ICSP Enable bit |
|
LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
|
|
LVP = ON |
0xFF |
Single-Supply ICSP enabled. |
|
|
BBSIZ -- Boot Block Size Select bits |
|
BBSIZ = BB256 |
0xCF |
256 Word. |
|
|
BBSIZ = BB512 |
0xDF |
512 Word. |
|
|
BBSIZ = BB1K |
0xFF |
1024 Word. |
|
|
XINST -- Extended Instruction Set Enable bit |
|
XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
|
|
XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
|
|
DEBUG -- Background Debugger Enable bit |
|
DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
|
|
DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
|
|
CONFIG5L (address:0x300008, mask:0x03) |
|
CP0 -- Code Protection bit |
|
CP0 = ON |
0xFE |
Block 0 code-protected. |
|
|
CP0 = OFF |
0xFF |
Block 0 not code-protected. |
|
|
CP1 -- Code Protection bit |
|
CP1 = ON |
0xFD |
Block 1 code-protected. |
|
|
CP1 = OFF |
0xFF |
Block 1 not code-protected. |
|
|
CONFIG5H (address:0x300009, mask:0xC0) |
|
CPB -- Boot Block Code Protection bitProtect Boot |
|
CPB = ON |
0xBF |
Boot block code-protected. |
|
|
CPB = OFF |
0xFF |
Boot block not code-protected. |
|
|
CPD -- Data EEPROM Code Protection bit |
|
CPD = ON |
0x7F |
Data EEPROM code-protected. |
|
|
CPD = OFF |
0xFF |
Data EEPROM not code-protected. |
|
|
CONFIG6L (address:0x30000A, mask:0x03) |
|
WRT0 -- Write Protection bit |
|
WRT0 = ON |
0xFE |
Block 0 write-protected. |
|
|
WRT0 = OFF |
0xFF |
Block 0 not write-protected. |
|
|
WRT1 -- Write Protection bit |
|
WRT1 = ON |
0xFD |
Block 1 write-protected. |
|
|
WRT1 = OFF |
0xFF |
Block 1 not write-protected. |
|
|
CONFIG6H (address:0x30000B, mask:0xE0) |
|
WRTC -- Configuration Register Write Protection bit |
|
WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) write-protected. |
|
|
WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) not write-protected. |
|
|
WRTB -- Boot Block Write Protection bit |
|
WRTB = ON |
0xBF |
Boot block write-protected. |
|
|
WRTB = OFF |
0xFF |
Boot block not write-protected. |
|
|
WRTD -- Data EEPROM Write Protection bit |
|
WRTD = ON |
0x7F |
Data EEPROM write-protected. |
|
|
WRTD = OFF |
0xFF |
Data EEPROM not write-protected. |
|
|
CONFIG7L (address:0x30000C, mask:0x03) |
|
EBTR0 -- Table Read Protection bit |
|
EBTR0 = ON |
0xFE |
Block 0 protected from table reads executed in other blocks. |
|
|
EBTR0 = OFF |
0xFF |
Block 0 not protected from table reads executed in other blocks. |
|
|
EBTR1 -- Table Read Protection bit |
|
EBTR1 = ON |
0xFD |
Block 1 protected from table reads executed in other blocks. |
|
|
EBTR1 = OFF |
0xFF |
Block 1 not protected from table reads executed in other blocks. |
|
|
CONFIG7H (address:0x30000D, mask:0x40) |
|
EBTRB -- Boot Block Table Read Protection bit |
|
EBTRB = ON |
0xBF |
Boot block protected from table reads executed in other blocks. |
|
|
EBTRB = OFF |
0xFF |
Boot block not protected from table reads executed in other blocks. |
|