PIC18F14K22LIN |
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CONFIG1H (address:0x300001, mask:0x27) |
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FOSC -- Oscillator Selection bits |
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FOSC = LP |
0xF0 |
LP oscillator. |
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FOSC = XT |
0xF1 |
XT oscillator. |
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FOSC = HS |
0xF2 |
HS oscillator. |
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FOSC = ERCCLKOUT |
0xF3 |
External RC oscillator, CLKOUT function on OSC2. |
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FOSC = ECCLKOUTH |
0xF4 |
EC, CLKOUT function on OSC2 (high). |
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FOSC = ECH |
0xF5 |
EC (high). |
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FOSC = ERC |
0xF7 |
External RC oscillator. |
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FOSC = IRC |
0xF8 |
Internal RC oscillator. |
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FOSC = IRCCLKOUT |
0xF9 |
Internal RC oscillator, CLKOUT function on OSC2. |
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FOSC = ECCLKOUTM |
0xFA |
EC, CLKOUT function on OSC2 (medium). |
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FOSC = ECM |
0xFB |
EC (medium). |
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FOSC = ECCLKOUTL |
0xFC |
EC, CLKOUT function on OSC2 (low). |
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FOSC = ECL |
0xFD |
EC (low). |
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PLLEN -- 4 X PLL Enable bit |
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PLLEN = OFF |
0xEF |
PLL is under software control. |
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PLLEN = ON |
0xFF |
Oscillator multiplied by 4. |
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PCLKEN -- Primary Clock Enable bit |
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PCLKEN = OFF |
0xDF |
Primary clock is under software control. |
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PCLKEN = ON |
0xFF |
Primary clock enabled. |
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FCMEN -- Fail-Safe Clock Monitor Enable |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Oscillator Switchover bit |
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IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
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IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x1F) |
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PWRTEN -- Power-up Timer Enable bit |
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PWRTEN = ON |
0xFE |
PWRT enabled. |
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PWRTEN = OFF |
0xFF |
PWRT disabled. |
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BOREN -- Brown-out Reset Enable bits |
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BOREN = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
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BOREN = ON |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
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BOREN = NOSLP |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
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BOREN = SBORDIS |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
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BORV -- Brown Out Reset Voltage bits |
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BORV = 30 |
0xE7 |
VBOR set to 3.0 V nominal. |
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BORV = 27 |
0xEF |
VBOR set to 2.7 V nominal. |
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BORV = 22 |
0xF7 |
VBOR set to 2.2 V nominal. |
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BORV = 19 |
0xFF |
VBOR set to 1.9 V nominal. |
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CONFIG2H (address:0x300003, mask:0x1F) |
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WDTEN -- Watchdog Timer Enable bit |
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WDTEN = OFF |
0xFE |
WDT is controlled by SWDTEN bit of the WDTCON register. |
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WDTEN = ON |
0xFF |
WDT is always enabled. SWDTEN bit has no effect. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xE1 |
1:1. |
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WDTPS = 2 |
0xE3 |
1:2. |
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WDTPS = 4 |
0xE5 |
1:4. |
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WDTPS = 8 |
0xE7 |
1:8. |
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WDTPS = 16 |
0xE9 |
1:16. |
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WDTPS = 32 |
0xEB |
1:32. |
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WDTPS = 64 |
0xED |
1:64. |
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WDTPS = 128 |
0xEF |
1:128. |
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WDTPS = 256 |
0xF1 |
1:256. |
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WDTPS = 512 |
0xF3 |
1:512. |
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WDTPS = 1024 |
0xF5 |
1:1024. |
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WDTPS = 2048 |
0xF7 |
1:2048. |
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WDTPS = 4096 |
0xF9 |
1:4096. |
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WDTPS = 8192 |
0xFB |
1:8192. |
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WDTPS = 16384 |
0xFD |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3H (address:0x300005, mask:0x88) |
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HFOFST -- HFINTOSC Fast Start-up bit |
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HFOFST = OFF |
0xF7 |
The system clock is held off until the HFINTOSC is stable. |
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HFOFST = ON |
0xFF |
HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. |
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MCLRE -- MCLR Pin Enable bit |
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MCLRE = OFF |
0x7F |
RA3 input pin enabled; MCLR disabled. |
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MCLRE = ON |
0xFF |
MCLR pin enabled, RA3 input pin disabled. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVREN -- Stack Full/Underflow Reset Enable bit |
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STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Single-Supply ICSP Enable bit |
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LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
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LVP = ON |
0xFF |
Single-Supply ICSP enabled. |
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BBSIZ -- Boot Block Size Select bit |
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BBSIZ = OFF |
0xF7 |
1kW boot block size. |
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BBSIZ = ON |
0xFF |
2kW boot block size. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x03) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFE |
Block 0 code-protected. |
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CP0 = OFF |
0xFF |
Block 0 not code-protected. |
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CP1 -- Code Protection bit |
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CP1 = ON |
0xFD |
Block 1 code-protected. |
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CP1 = OFF |
0xFF |
Block 1 not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot block code-protected. |
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CPB = OFF |
0xFF |
Boot block not code-protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x03) |
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WRT0 -- Write Protection bit |
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WRT0 = ON |
0xFE |
Block 0 write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 not write-protected. |
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WRT1 -- Write Protection bit |
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WRT1 = ON |
0xFD |
Block 1 write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers not write-protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot block write-protected. |
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WRTB = OFF |
0xFF |
Boot block not write-protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x03) |
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EBTR0 -- Table Read Protection bit |
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EBTR0 = ON |
0xFE |
Block 0 protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit |
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EBTR1 = ON |
0xFD |
Block 1 protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot block protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot block not protected from table reads executed in other blocks. |
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